This invention relates to the architecture of a floating-point unit in a computer and, more particularly, to methods and apparatus for controlling the exponent range during floating-point calculations.
Floating-point units for performing floating arithmetic in a computer typically include a floating-point computation unit, a set of floating-point registers for holding operands, intermediate results and the like, and a floating-point status register. The floating-point computation unit is typically pipelined so that different operations of different floating-point calculations may be performed simultaneously. The floating-point status register includes control information, such as precision control and rounding control, that controls the floating-point calculation. In addition, the floating-point status register includes flag information, such as overflow and zero divide flags which record exceptions that occurred during a floating-point calculation.
Floating-point units are typically configured for compliance with ANSI/IEEE floating-point standard no. 754-1985. This standard specifies floating-point data types, various arithmetic and other operations, and handling of exceptions. It is desirable to provide a floating-point unit which meets the IEEE floating-point standard in all respects and which has additional features that overcome drawbacks in the prior art and thereby enhance performance.
The conventional floating-point status register is a hardware register that contains control information and flag information as described above. The control information is set by software, and the flag information is set in response to execution of a floating-point calculation. Conventionally, the control information is modified by copying the contents of the floating-point status register to a general purpose register, modifying the contents of the general purpose register and then writing the contents of the general purpose register back to the floating-point status register. The flag information in the floating-point status register may be cleared in a similar manner. Thus, the operations of updating control information and clearing flag information are relatively time-consuming. Furthermore, when the control information in the floating-point status register is updated, it is necessary to flush the pipelined floating-point computation unit, thereby aborting partially completed calculations and degrading performance. Because of these drawbacks, frequent updating of the floating-point status register is typically avoided.
The execution of speculative operations is a known technique for enhancing processor performance. In order to maximize utilization of a processor, instructions that appear later in a program may be scheduled for execution in parallel with earlier instructions, if the operands necessary for execution are available. Because branch instructions are usually present in the program, it may not be possible to determine in advance whether an instruction will require execution. However, if resources of the processor are otherwise idle, the performance of the processor may be improved by executing instructions speculatively, even though execution of those instructions may later be determined to be unnecessary. Execution of an instruction that follows a branch instruction before execution of the branch instruction is known as speculative execution. If the program ultimately requires execution of the instruction that was executed speculatively, an improvement in performance is obtained. If execution of the speculative instruction is not required, the result is discarded.
The floating-point status register contains flag information in the form of flag bits, or simply xe2x80x9cflagsxe2x80x9d. The flags record exceptions that occur during execution of a floating-point calculation. Exceptions may also create interruptions. In the case of speculative execution, it is undesirable to report an exception immediately because the result of the speculative execution may later be discarded. Nonetheless, floating-point units typically handle flags for speculative operations in the same manner as nonspeculative operations.
One of the exceptions that is recorded in the flag information is an overflow exception, where the exponent in the result of the calculation is outside a specified range. The range may be established by the memory format used to store floating-point numbers or by the user of the result. However, the floating-point unit may have the capability of handling floating-point numbers which are outside the range that causes the reporting of an overflow exception. This may give rise to the reporting of overflow exceptions unnecessarily. For example, floating-point calculations typically involve several operations. In certain calculations, the result of an intermediate operation may produce an overflow exception, even though the final result would not produce an overflow exception if the calculation was permitted to continue. It is desirable to avoid reporting exceptions unnecessarily, since execution may be delayed or terminated.
Another aspect of handling floating numbers during floating-point calculations relates to xe2x80x9cbig endianxe2x80x9d and xe2x80x9clittle endianxe2x80x9d formats. In big endian format, a data word is stored in memory with its most significant byte corresponding to the most significant byte of the memory word. In little endian format, a data word is stored in memory with its least significant byte corresponding to the most significant byte of the memory word. A processor may be required to handle both formats efficiently.
It is desirable to provide floating-point architectures which alleviate or eliminate one or more of the above-described drawbacks.
According to a first aspect of the invention, a method is provided for performing a floating-point calculation in a computer comprising a floating-point computation unit, a memory and floating-point registers. The method comprises the steps of performing a non-final operation of the floating-point calculation in the floating-point computation unit, and generating a non-final result. The non-final operation of the floating-point calculation is controlled so that an exception is generated if the exponent of the non-final result is incompatible with a first exponent range. A final operation of the floating-point calculation is performed in the floating-point computation unit, and a final result is generated. The final operation of the floating-point calculation is controlled so that an exception is generated if the exponent of the final result is incompatible with a second exponent range. The first exponent range is wider than the second exponent range. The first exponent range may comprise a register exponent range of a register format used in the floating-point registers. The second exponent range may comprise a memory exponent range of a memory format used in the memory.
Preferably, the non-final operation and the final operation are controlled in response to the state of a widest range exponent bit. In one embodiment, the computer further comprises a floating-point status register, and the widest range exponent bit is stored in the floating-point status register. The floating-point status register may comprise two or more status fields, each having a widest range exponent bit. Different operations of the floating-point calculation may be associated with different ones of the status fields. The non-final operation may be associated with a status field having the widest range exponent bit set, and the final operation may be associated with a status field having the widest range exponent bit reset.
In another embodiment, the non-final operation and the final operation may be controlled in response to the state of a widest range exponent bit contained in a corresponding instruction.
According to another aspect of the invention, apparatus is provided for performing a floating-point calculation. The apparatus comprises a computer including a floating-point computation unit, a memory and floating-point registers. The apparatus further comprises means for performing a non-final operation of the floating-point calculation in the floating-point computation unit and generating a non-final result, means for controlling the non-final operation so that an exception is generated if the exponent of the non-final result is incompatible with a first exponent range, means for performing a final operation of the floating-point calculation in the floating-point computation unit and generating a final result, and means for controlling the final operation so that an exception is generated if the exponent of the final result is incompatible with a second exponent range. The first exponent range is wider than the second exponent range.